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 | SAMSUNG/TMTC 512MB PC2100 266MHZ 200 PIN DDR SODIMM - GUARANTEED COMPATIBLE"""""" Memory Upgrade for your MSI Computer Corporation Mega Book S270 Notebook (1013-014)Free Same Day ShippingFull 30 Day Money Back Guarantee with free shipping both ways.Unlimited Lifetime WarrantyGuaranteed compatible and tested for MSI Computer Corporation Mega Book S270 Notebook (1013-014) Works Great in All Pentium, Apple, and AMD Athlon Notebooks, i.e. Dell Inspiron 8500, HP ZT1175, please see below for a more complete list 512MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval""" (less) | $39  MemorySuppliers.com |
|  | SAMSUNG/TMTC 512MB PC2100 266MHZ 200 PIN DDR SODIMM - GUARANTEED COMPATIBLE"""""" Memory Upgrade for your MSI Computer Corporation Mega Book S270 Notebook (1013-015)Free Same Day ShippingFull 30 Day Money Back Guarantee with free shipping both ways.Unlimited Lifetime WarrantyGuaranteed compatible and tested for MSI Computer Corporation Mega Book S270 Notebook (1013-015) Works Great in All Pentium, Apple, and AMD Athlon Notebooks, i.e. Dell Inspiron 8500, HP ZT1175, please see below for a more complete list 512MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval""" (less) | $39  MemorySuppliers.com |
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