needed,support windows 2000/me/xp/vista.Upgrade your notebook today! Features: General Features: Emergency Eject Hole Activity LED Enhanced-IDE (ATAPI) model Hot Plug & Play 2 MB buffer Writing Speed: 6x DVD+R DL (Double Layer), 4x DVD-R DL (Dual), 5x DVD-RAM, 8x DVD+R, 8x DVD-R, 24x CD-R, 8x DVD+RW, 6x DVD-RW, 24x CD-RW Reading Speed: 5x DVD-RAM, 8x DVD+R, 8x DVD-R, 8x DVD-ROM, 24x CD-R, 24x CD-ROM, 24x CD-RW, 6x DVD-RW, 8x DVD+RW Supported Formats: DVD+R/RW, DVD-R/RW, CD-Audio, CD-DA, CD-ROM, CD-ROM XA, CD-R, CD-RW, CD-I, Photo-CD, Video CD, CD Extra, CD-G, CD Text, DVD-ROM, DVD-RAM, DVD-Video Regulatory Approvals: CE, MIC, TUV, C-Tick, BSMI Compatible with follow models: Sony Vaio PCG K Series: PCG-K12, PCG-K13, ...  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)

All Pentium 4 and AMD Athlon Notebooks 1GB/1024MB Non-ECC 200 pin Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ??0.2V, VDDQ = +2.5V ??0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes"""  (less)