well as CD-ROM, CD-R and 2.6/4.7 GB DVD-RAM discs.  (less)

Server (353829-001) 2GB ECC optimized pinout Registered CAS Latency 2.5 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6???s maximum average periodic refresh interval"""  (less)

Server (353829-001) 1024MB (128 x 64) ECC optimized pinout Registered CAS Latency 2.5 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6???s maximum average periodic refresh interval Partial Compatibility List: ABIT - KG7/KG7-RAID ASUS - CUV266-DLS DDR Iwill - DVD266/DVD266-R Tyan Computers - Tyan Thunder K7 (S2462) UNG/NGM Tyan Computers - Tyan Tiger MP (S2460)"""  (less)

Meg x 64) ECC optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

(64 Meg x 64) ECC optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

Meg x 64) ECC optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

Meg x 64) ECC optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

Meg x 64) ECC optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

Meg x 64) ECC optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

Meg x 64) ECC optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 256MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 256MB (32 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 256MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 256MB (32 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 256MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 256MB (32 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 256MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 256MB (32 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 256MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 256MB (32 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 256MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 256MB (32 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6??s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 128MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 128MB (16 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 128MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 128MB (16 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 128MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 128MB (16 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 128MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 128MB (16 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 128MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 128MB (16 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)

PC-2100 CL2.5 128MB 184pin Memory made by MICRON. This is a very high quality memory with LIFETIME WARRANTY Compatible with all computer using DDR standard. (please note DDR memory is not backward-compatible with SDRAM (PC66,PC100,PC133) and requires motherboards and systems especially designed for DDR266. DDR266 SDRAM provides twice the memory bandwidth of earlier PC100 and PC133 DRAM solutions. This bandwidth improvement is reached by transferring data on both the rising and falling edge of the clock cycle, hence the name "Double Data Rate." 128MB (16 Meg x 64) ECC-optimized pinout 184-pin, dual in-line memory modules (DIMM) Gold leads Phase-lock loop (PLL) clock driver to reduce loading VDD = +2.5V ???0.2V, VDDQ = +2.5V ???0.2V VDDSPD = +2.5V to +3.3V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6 ???s maximum average periodic refresh interval"""  (less)